The present invention relates to a matrix display device using a multiplex matrix display panel.
Various sorts of display cells for the matrix display device, such as liquid crystal cells, electrochromic cells, a plasma display, a fluorescent display tube, LED's, PLZT cells and electroluminescence cells, have been known. By way of example, the principle of a liquid crystal display device is illustrated in FIG. 1, in which the liquid crystal 103 is held between a pair of substrates 101 and 102 at least one of which is transparent, and a predetermined voltage is applied between transparent electrodes 104 and 105 formed on the opposing surfaces of the substrates 101 and 102 to cause an electrooptical change in liquid crystal molecules. The relation between an effective voltage applied across the transparent electrodes 104 and 105 and the amount of transmitted light is shown in FIG. 2, in which V.sub.S and V.sub.NS represent threshold voltages. In the liquid crystal matrix display device, picture cells defined at the crosspoints of the transparent electrodes 104 and 105 are generally arranged in matrix form and characters or graphic patterns are displayed by selecting the effective voltages applied to the respective picture cells.
In such a matrix display device, in order to fire a number of picture cells with a high contrast, a multiplex matrix system or an alternate multiplex matrix system has been proposed. By way of example, a multi-matrix or duplex matrix system display device is explained with reference to FIGS. 3 to 5. Configurations shown in FIGS. 3 and 5 are disclosed in Japanese patent application Laid-Open Nos. 120230/78 and 106189/79, respectively.
Referring to FIG. 3, numeral 100 denotes an image data circuit which comprises a video signal input terminal 1, an A-D converter 2 and a timing control circuit 3. Column electrode drive circuits 4 and 5 comprise line memories 41 and 51, latch registers 42 and 52 and modulators 43 and 53, respectively. Numeral 6 denotes a row electrode drive circuit. A matrix display panel 7 has an electrooptical effect material, such as a liquid crystal or an electroluminescence material, filled in between a pair of substrates 8 and 9. The first substrate 8 has I row electrodes X.sub.1 -X.sub.I and the second substrate 9 has J A-column electrodes Y.sub.A1 -Y.sub.AJ and J B-column electrodes Y.sub.B1 -Y.sub.BJ. The column electrodes are electrically divided into two groups which form J display columns Y.sub.1 -Y.sub.J. Accordingly, 2I rows by J columns of picture cells are defined at the crosspoints of the row electrodes, and the column electrodes with the i-th row electrode X.sub.i (i=1, 2, . . . I) being connected to the (2i-1) the row picture cell and the (2i)th row picture cell. The A-column electrode Y.sub.Aj of the i-th column Y.sub.j (j=1, 2, . . . J) is connected to the picture cells on the odd numbered rows ((2i-1)th row) and the B-column electrode Y.sub.Bj is connected to the picture cells on the even numbered rows ((2i)th row).
Referring to FIG. 4a, circled numerals under a video signal VD indicate row numbers of a scan line of the video signal.
The video signal VD as shown in FIG. 4a is applied to the video signal input terminal 1. The A-D converter 2 receives the video signal VD and a sampling clock CP.sub.1 and converts the video signal VD to a digital signal SD in synchronism with the sampling clock CP.sub.1. The timing control circuit 3 extracts a synchronizing signal from the video signal VD to generate the sampling clock CP.sub.1, write clocks CP.sub.A and CP.sub.B and a strobe pulse STB for controlling the display device.
The line memory 41 receives the digital video signal SD and the write clock CP.sub.A which is generated at the odd row period of the scan line and serially stores one scan line of video data in synchronism with the clock CP.sub.A. The line memory 51 receives the digital video signal SD and the write clock CP.sub.B which is generated at the even row period of the scan line and stores one scan line of video data in synchronism with the clock CP.sub.B. Accordingly, the odd rows of the scan line of video data are written into the line memory 41 while the even rows of the scan line of video data are written into the line memory 51. As shown in FIG. 4a, the first row of the scan line of video data is first written into the line memory 41 and then the second row of the scan line of video data is written into the line memory 51.
The strobe pulse STB is generated when the even rows of the scan line of video data have been written into the line memory 51. The latch registers 42 and 52 receive the video data stored in the line memories 41 and 51, respectively, and the strobe pulse STB and parallelly latch the video data from the line memories 41 and 51, respectively, in synchronism with STB.
The modulator 43 receives the odd rows of the scan line of video data latched in the latch register 42 and supplies column electrode drive signals V.sub.YAj (j=1, 2, . . . J) to the column electrodes Y.sub.Aj for modulating the brightnesses of the picture cells. Similarly, the modulator 53 receives the even rows of the scan line of video data latched in the latch register 52 and supplies column electrode drive signal V.sub.YBj to the column electrodes Y.sub.Bj.
The row electrode drive circuit 6 receives the strobe pulse STB and supplies row electrode drive signals V.sub.Xi (i=1, 2, . . . I) to the row electrodes X.sub.i. The row electrode drive signals V.sub.Xi are generated in such a manner that only one of the row electrodes X.sub.i is selected and other row electrodes are not selected at a time and the row electrodes X.sub.i are sequentially selected one at a time in synchronism with the strobe pulse STB.
Specific waveforms of the row electrode drive signal V.sub.Xi and the column electrode drive signals V.sub.YAj and V.sub.YBj vary depending on particular electrooptical material used as the display medium.
The row electrode drive signal V.sub.X and the column electrode drive signal V.sub.Y for the liquid crystal display medium are shown in FIG. 4b. A constant a is selected to be equal to or close to .sqroot.I+1 where I is the number of the row electrodes X.sub.i, and V.sub.o is a maximum amplitude of a voltage V.sub.x -V.sub.y applied to the picture cell. The voltage V.sub.o is selected to meet the following relation: ##EQU1## where V.sub.TH is a threshold voltage of the liquid crystal.
Each of the scan electrodes X.sub.i is selected in every I-th cycle. The brightness of the picture cell is determined by a ratio T.sub.A /T of the column electrode drive signal V.sub.Y. When T.sub.A =T, the brightness of the picture cell is maximum, and when T.sub.A =0 it is minimum. Accordingly, by controlling the ratio T.sub.A /T, tone of the displayed image can be controlled.
Referring to FIG. 4a, the video data written into the line memories 41 and 51 at the first and second rows of the scan line of video signal VD, respectively, are transferred to the latch registers 42 and 52 in response to the strobe pulse STB generated at the end of the second row of the scan line and modulated into the column electrode drive signals V.sub.YAj and V.sub.YBj by the modulator 43 and 53 so that the first and second rows of the video data are supplied to the column electrodes Y.sub.Aj and Y.sub.Bj. During this period, the third and fourth rows of the scan line of video signal VD are written into the line memories 41 and 51 as the next video data. The row electrode drive circuit 6, at this time, generates the row electrode drive signal V.sub.Xi to select the first row electrode X.sub.1 so that the first and second rows of the picture cells on the column Y.sub.1 are fired.
At the end of the fourth column of the scan line of video signal VD, the strobe pulse STB is again generated and the column electrode drive signals V.sub.YAj and V.sub.YBj drive the third and fourth rows of the video signal VD and the row electrode drive signal V.sub.Xi selects the second row electrode X.sub.2 so that the third and fourth rows of the picture cells on the column Y.sub.i are fired. Similar operations are repeated to fire other picture cells.
FIG. 5 shows a prior art example in which lead terminals of the column electrodes Y.sub.Aj and Y.sub.Bj and the column electrode circuits 4 and 5 are collected on one side of the one substrate 9 of the matrix display panel 7 in order to reduce the size of the device shown in FIG. 3. In FIG. 5, the like numerals to those of FIG. 3 denote like elements.
As shown in FIG. 5, where the terminals of the different column electrodes Y.sub.Aj and Y.sub.Bj are arranged on the same side of the matrix display panel 7, the signal lines of the column electrodes Y.sub.Aj and Y.sub.Bj and the column electrode drive circuits 4 and 5 cross each other. Accordingly, they cannot be wired by a flat cable, but a multi-layer printed circuit board is required, which results in the increase of the manufacturing cost.